Imec Presents Patterning Solutions for N5-equivalent Metal Layers

Publication date : 27/02/2017

As an alternative to the cost-prohibitive and complex self-aligned quadruple patterning (SAQP) + immersion triple block patterning for the 32nm metal layer (M2), imec has developed two approaches that include exposure on ASML’s NXE:3300B EUV-scanner. The primary solution involves completing the SAQP with a single EUV blocking step, which offers a 20 percent wafer cost reduction over the full immersion approach. The alternate approach relies on EUV for a single patterning step, replacing both the SAQP and triple blocking steps.  This adds an additional cost reduction, but has more implementation challenges than the SAQP+EUV block solution. As pitch-only scaling becomes a burden in technology node transition, imec’s solutions have been complemented by co-optimizing the technology and the design libraries resulting in significantly lower area while lessening the burden in pitch-only scaling. This allows a full node definition with fixed wafer cost increase with more area reduction.

As part of the solution, imec and ASML created a 2D OPC full-chip model, which was then used to design and fabricate the EUVL block mask. Also for the etch process, solutions have been found that meet the requirements.  As for the mask pellicles, imec reports on work for 250W exposure membranes, investigating a promising group of materials based on carbon nanotubes (CNT).

Lastly, the SAQP and block structures have been characterized in detailed morphological studies, assessing pattern fidelity and variability. At a 32nm pitch, even minor process variations in EUVL may have significant impact on device performance. Such variations are due to overlay and critical dimension uniformity issues, in addition to EUVL-specific effects such as shadowing, M3D, flare and stochastic effects. Imec simulated and measured these effect on the wafers, demonstrating the suitability of the proposed solutions and identifying approaches to fine-tune processing computationally, e.g. further refining the OPC.

About imec

Imec is the world-leading research and innovation hub in nano-electronics and digital technologies. The combination of our widely acclaimed leadership in microchip technology and profound software and ICT expertise is what makes us unique. By leveraging our world-class infrastructure and local and global ecosystem of partners across a multitude of industries, we create groundbreaking innovation in application domains such as healthcare, smart cities and mobility, logistics and manufacturing, and energy. 

As a trusted partner for companies, start-ups and universities we bring together close to 3,500 brilliant minds from over 70 nationalities. Imec is headquartered in Leuven, Belgium and also has distributed R&D groups at a number of Flemish universities, in the Netherlands, Taiwan, USA, China, and offices in India and Japan. In 2015, imec's revenue (P&L) totaled 415 million euro and of iMinds which is integrated in imec as of September 21, 2016 52 million euro. Further information on imec can be found at www.imec-int.com.

Imec is a registered trademark for the activities of IMEC International (a legal entity set up under Belgian law as a "stichting van openbaar nut”), imec Belgium (IMEC vzw supported by the Flemish Government), imec the Netherlands (Stichting IMEC Nederland, part of Holst Centre which is supported by the Dutch Government), imec Taiwan (IMEC Taiwan Co.) and imec China (IMEC Microelectronics (Shanghai) Co. Ltd.) and imec India (Imec India Private Limited), imec Florida (IMEC USA nanoelectronics design center).

Contact :

imec : Hanne Degans, Press officer and communications specialist, T: +32 16 28 17 69 // Mobile : +32 486 06 51 75 // Email: Hanne.Degans@imec.be